<html><head><meta http-equiv="Content-Type" content="text/html; charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class=""><h1 align="center" style="margin: 0cm; text-align: center; line-height: 24.4pt;" class="">CALL FOR PAPERS IEEE Micro (Magazine)  Special Issue on<o:p class=""></o:p></h1><h3 align="center" style="margin: 0cm; text-align: center; line-height: 22.5pt;" class=""> Artificial Intelligence at the Edge<o:p class=""></o:p></h3><div class="">  </div>Artificial intelligence (AI) algorithms require powerful and efficient computer architectures for two distinct tasks: training and inference. The first is extremely compute- and memory-intensive, and in some cases can take days or weeks to complete. The latter usually implies real-time performance. As an increasing number of smart devices come online, performing more AI inference at the edge (far away from the cloud), they have the power to enable lower latency, greater privacy, better data governance, and higher availability when compared to cloud/datacenter-based inference. Also, training can be favored by adopting new federated learning computational models that perform part of the training concurrently on each edge node and merge parameters on the cloud/server later. The thorough understanding of the interaction of hardware and software in edge architectures creates a unique opportunity to innovate the ever-increasing energy efficiency, performance, and usability of AI systems at the edge.<o:p class=""></o:p> <o:p class=""></o:p>This special issue of IEEE Micro will explore academic and industrial research on topics that combine AI and edge computing. Contributions should relate to the design, performance, or application of microprocessors and microcomputers.<o:p class=""></o:p><table class="MsoNormalTable" border="0" cellspacing="0" cellpadding="0" width="100%" style="width: 1031px; background-color: white; border-collapse: collapse;"><tbody class=""><tr class=""><td style="padding: 0cm;" class=""></td></tr></tbody></table><table class="MsoNormalTable" border="0" cellspacing="0" cellpadding="0" width="100%" style="width: 1031px; background-color: white; border-collapse: collapse;"><tbody class=""><tr class=""><td valign="top" style="padding: 0cm;" class=""><table class="MsoNormalTable" border="0" cellspacing="0" cellpadding="0" align="left" width="100%" style="width: 1031px; border-collapse: collapse;"><tbody class=""><tr class=""><td style="padding: 6.75pt 13.5pt;" class=""><table class="MsoNormalTable" border="1" cellspacing="0" cellpadding="0" width="100%" style="width: 994px; border-collapse: collapse; border: none;"><tbody class=""><tr class=""><td valign="top" style="border: 1pt solid rgb(167, 192, 201); padding: 13.5pt;" class="">Topics of interest include (but are not limited to):<o:p class=""></o:p><ul type="disc" class=""><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">Digital or analog AI systems at the edge<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">Low-power neural processing engines<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">Energy efficiency of AI systems at the edge<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">DSL and parallel programming models for AI systems at the edge<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">FPGAs and low-power GPUs for AI at the edge<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">Customized accelerator architectures and functional unit design<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">Methods for efficient reconfigurability and adaptability at the edge<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">High-level synthesis design of customized AI engines at the edge<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">Emerging memory technologies for edge AI, such as processing-in-memory systems<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">Computer systems abstractions to federated learning models<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">Computation and communication tradeoffs in federated learning models<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">Tools and libraries to support AI systems at the edge, such as IoT, virtual reality/augmented reality (VR/AR) systems, and wearables<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">AI systems for big-data processing at the edge, such as bioinformatics, genomics, digital agriculture, and weather prediction<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">Formal methods and techniques for data privacy in medical data, finance data, etc.<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">Security implications of AI computing at the edge<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">Sensor preprocessing and platform integration<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">Techniques and analysis of quantization and network pruning<o:p class=""></o:p></li><li class="MsoNormal" style="color: rgb(14, 13, 13); line-height: 15.75pt;">Real-time performance, accuracy, and system complexity constraint analysis<o:p class=""></o:p></li></ul></td></tr></tbody></table></td></tr></tbody></table></td></tr></tbody></table><table class="MsoNormalTable" border="0" cellspacing="0" cellpadding="0" width="100%" style="width: 1031px; background-color: white; border-collapse: collapse;"><tbody class=""><tr class=""><td valign="top" style="padding: 6.75pt 0cm 0cm;" class=""><table class="MsoNormalTable" border="0" cellspacing="0" cellpadding="0" align="left" width="100%" style="width: 1031px; border-collapse: collapse;"><tbody class=""><tr class=""><td valign="top" style="padding: 0cm 13.5pt 6.75pt;" class="">Important Dates: Submission deadline: February 15, 2022 Initial notifications: May 17, 2022 Revised papers due: June 7, 2022 Final notifications: July 12, 2022 Final versions due: July 26, 2022 Publication: September/October 2022. Submission Guidelines:<o:p class=""></o:p>Manuscripts should not exceed 5,000 words including references, with each average-size figure counting as 250 words toward this limit. Please include all figures and tables, as well as a cover page with author contact information (name, postal address, phone, fax, and email address) and a 200-word abstract. Submitted manuscripts must not have been previously published or be currently submitted for publication elsewhere, and all manuscripts must be cleared for publication. All previously published papers must have at least 30% new content compared to any conference (or other) publication. Acceptable file formats include Microsoft Word and PDF. Please read the Author Information page before submitting. When you are ready to submit, go to ScholarOne Manuscripts at <a href="https://mc.manuscriptcentral.com/micro-cs" class="">https://mc.manuscriptcentral.com/micro-cs</a>.<o:p class=""></o:p><div style="line-height: 18pt;" class="">  </div>Questions?<o:p class=""></o:p>Contact the guest editors Gabriel Falcao and Joseph R. Cavallaro concerning the scope of this special issue at <a href="mailto:micro5-22@computer.org" class="">micro5-22@computer.org</a>, or for general questions about IEEE Micro the Editor-in-Chief Lizy John at <a href="mailto:ljohn@ece.utexas.edu" class="">ljohn@ece.utexas.edu</a>. For questions about the ScholarOne submission system, contact the IEEE Micro magazine assistant at <a href="mailto:micro-ma@computer.org" class="">micro-ma@computer.org</a>.<o:p class=""></o:p> Warm regards from Houston and Coimbra,<o:p class=""></o:p><div style="line-height: 18pt;" class="">  </div>Guest editors:Gabriel FalcaoJoseph R. Cavallaro<o:p class=""></o:p><div class=""> </div></td></tr></tbody></table></td></tr></tbody></table></body></html>